To ensure that an NMOS transistor operates troublefree to the extent possible even at operating voltages below the substrate potential, a well-in-well technology is applied where a second p-conducting region in the form of a p-well is placed into a CMOS process within a first n-conducting region, i. e. an n-well. A section of such a transistor is shown in FIG. 1. The transistor comprises a weakly p-doped semiconducting substrate 1 into which an n-well 2 is placed by means of diffusion. Into this n-conducting region a p-conducting region, i. e. a p-well 4, is placed by diffusion from the top side 3 of the substrate 1. The p-conducting region 4 is limited on all sides by a field oxide layer 5 on the top side 3 of the substrate 1 with the limiting edge of the p-well towards the n-well 2 being located below the field oxide layer 5 due to the "underdiffusion". In the p-well 4 degenerated n.sup.+ -regions 6 and 7 for source and drain are placed between which the gate oxide layer 8 and the gate electrode 9 are located.
By application of such an NMOS transistor design the following is achieved:
electrical isolation of the NMOS transistor from the substrate by two pn-transitions, PA1 prevention of the substrate effect owing to the possibility to apply the potential of the p-well to the source potential of the transistor and PA1 operation of the p-well and the transistor below substrate potential. PA1 An existing n-well CMOS process requires placing of an additional p-well with complete modification of the process start (well diffusion/field oxidation/temperature balance); PA1 when Epi substrates are used, the penetration depth of the n-well is limited by outdiffusion of the substrate doping; PA1 in the case of a diffused p-well the surface concentration (threshold voltage of the NMOS transistor) and the doping profile are coupled to each other in the depth (isolation/voltage sustaining capability of the NMOS transistor towards the n-well); matching of the well dopings/diffusions means at the same time influence on almost all other components. PA1 maintaining the previous well concept (diffused n-well) and PA1 producing the p-well by an (existing) implantation, PA1 with no modification of the thermal balance (compatibility, modular process option) being carried out.
However, the above transistor design requires suitable wells with the n-well having to be considerably deeper than the p-well in order to provide the necessary isolation features and voltage sustaining capabilities. When the usual diffused wells are used, this means a considerable process expenditure: